Learning Computer Architecture with Raspberry Pi

Eben Upton is one of the co-creators of the Raspberry Pi, driven by the desire to create a new generation of developers capable of making an effective contribution to the field. Eben is also a co-author of the Raspberry Pi User Guide. Jeff Dunteman is a veteran tech author and a co-founder of Coriolis Press. His previous publications include Assembly Language Step By Step and Jeff Dunteman's Wi-Fi Guide.

Introduction 1 Cambridge 1 Cut to the Chase 3 The Knee in the Curve 4 Forward the Foundation 5 Chapter 1 The Shape of a Computer Phenomenon 7 Growing Delicious, Juicy Raspberries 7 System-on-a-Chip 10 An Exciting Credit Card-Sized Computer 12 What Does the Raspberry Pi Do? 14 Meeting and Greeting the Raspberry Pi Board 14 GPIO Pins 15 Status LEDs 16 USB Receptacles 18 Ethernet Connection 18 Audio Out 19 Composite Video 21 CSI Camera Module Connector 21 HDMI 22 Micro USB Power 22 Storage Card 23 DSI Display Connection 24 Mounting Holes 25 The Chips 25 The Future 25 Chapter 2 Recapping Computing 27 The Cook as Computer 28 Ingredients as Data 28 Basic Actions 30 The Box That Follows a Plan 31 Doing and Knowing 31 Programs are Data 32 Memory 33 Registers 34 The System Bus 36 Instruction Sets 36 Voltages, Numbers and Meaning 37 Binary: Counting in 1s and 0s 37 The Digit Shortage 40 Counting and Numbering and 0 40 Hexadecimal as a Shorthand for Binary 41 Doing Binary and Hexadecimal Arithmetic 43 Operating Systems: The Boss of the Box 44 What an Operating System Does 44 Saluting the Kernel 46 Multiple Cores 46 Chapter 3 Electronic Memory 47 There Was Memory Before There Were Computers 47 Rotating Magnetic Memory 48 Magnetic Core Memory 50 How Core Memory Works 50 Memory Access Time 52 Static Random Access Memory (SRAM) 53 Address Lines and Data Lines 54 Combining Memory Chips into Memory Systems 56 Dynamic Random Access Memory (DRAM) 59 How DRAM Works 60 Synchronous vs. Asynchronous DRAM 62 SDRAM Columns, Rows, Banks, Ranks and DIMMs 64 DDR, DDR2 DDR3 and DDR4 SDRAM 66 Error-Correcting Code (ECC) Memory 69 The Raspberry Pi Memory System 70 Power Reduction Features 70 Ball-Grid Array Packaging 71 Cache 72 Locality of Reference 72 Cache Hierarchy 72 Cache Lines and Cache Mapping 74 Direct Mapping 76 Associative Mapping 78 Set-Associative Cache 79 Writing Cache Back to Memory 81 Virtual Memory 81 The Virtual Memory Big Picture 82 Mapping Virtual to Physical 83 Memory Management Units: Going Deeper 84 Multi-Level Page Tables and the TLB 88 The Raspberry Pi Swap Problem 88 Watching Raspberry Pi Virtual Memory 90 Chapter 4 ARM Processors and Systems-on-a-Chip 93 The Incredible Shrinking CPU 93 Microprocessors 94 Transistor Budgets 95 Digital Logic Primer 95 Logic Gates 96 Flip-Flops and Sequential Logic 97 Inside the CPU 99 Branching and Flags 101 The System Stack 102 System Clocks and Execution Time 105 Pipelining 106 Pipelining in Detail 108 Deeper Pipelines and Pipeline Hazards 109 The ARM11 Pipeline 112 Superscalar Execution 113 More Parallelism with SIMD 115 Endianness 118 Rethinking the CPU: CISC vs. RISC 119 RISC's Legacy 121 Expanded Register Files 122 Load/Store Architecture 122 Orthogonal Machine Instructions 123 Separate Caches for Instructions and Data 123 ARMs from Little Acorns Grow 124 Microarchitectures, Cores and Families 125 Selling Licenses Rather Than Chips 125 ARM11 126 The ARM Instruction Set 126 Processor Modes 129 Modes and Registers 131 Fast Interrupts 137 Software Interrupts 137 Interrupt Priority 138 Conditional Instruction Execution 139 Coprocessors 142 The ARM Coprocessor Interface 143 The System Control Coprocessor 143 The Vector Floating Point (VFP) Coprocessor 144 Emulating Coprocessors 145 ARM Cortex 145 Multiple-Issue and Out-Of-Order Execution 146 Thumb 2 147 Thumb EE 147 big.LITTLE 147 The NEON Coprocessor for SIMD 148 ARMv8 and 64-Bit Computing 148 Systems on a Single Chip 150 The Broadcom BCM2835 SoC 150 Broadcom's Second- and Third-Generation SoC Devices 151 How VLSI Chips Happen 151 Processes, Geometries and Masks 152 IP: Cells, Macrocells and Cores 153 Hard and Soft IP 154 Floorplanning, Layout and Routing 154 Standards for